1. Field of the Invention
The present invention relates to microprocessor of the look-ahead control type, which is capable of performing a high speed instruction excution.
2. Description of the Prior Art
In a microprocessor of the present look-ahead control type, pipeline processing is performed in order to realize high speed instruction execution as well as realizing multifunction and high speed performance of the system, by employing a microprogram control system.
For the purpose of increasing the decoding efficiency of macroinstructions in these microprocessors described above, it is a general later from macroinstructions which are currently being executed. In this case, the macroinstructions read out of an external memory are temporarily stored in a buffer memory within an instruction decoder of the microprocessor and the macroinstructions thus stored are read out of the buffer memory and are then decoded.
FIG. 1 shows a block diagram of the conventional microprocessor for performing the decoding operation described above. Namely, in FIG. 1, the microprocessor 1 comprises a decoder 3 for decording the macroinstructions, an instruction execution unit 5 for executing the decoded instructions and a bus controller 7 for controlling an external data bus 100 in accordance with a demand for using the bus by both the decoder 3 and the instruction execution unit 5.
The decoder 3 includes therein a buffer 9 for temporarily storing a plurality of macroinstructions. The buffer 9 has a memory capacity N times larger than the amount of data which can be transferred by the external data bus 100 at a time macroinstructions which are to be executed after the instructions currently being executed have been completed are transferred at a time and are stored therin in accordance with the transfer capability of the external data bus 100. The macroinstructions thus stored in the buffer 9 are decoded by the decoder 3 after they are successively read out, and the macroinstructions thus decoded are applied to the instruction execution unit 5 through an internal bus 200.
Furthermore, when the macroinstructions are read out of the buffer 9 and any vacancy occurs in the buffer 9 for storing the amount of data amount which can be transferred at a time by the external data bus 100, the decoder 3 demands to of the bus controller 7 a fetch of the macroinstructions via a signal line 300, the fetch being a read-out of the macroinstructions from an external memory (not shown) which is connected to the external data bus 100.
The instruction excution unit 5 is for executing the macroinstructions which are decoded by the decoder 3 and applied thereto via the internal bus 200. The instruction execution unit 5, when using the external data bus 100 in association with the instruction executions, suplies the bus-controller 7 with a demand for using the external data bus 100 via the signal line 400.
The bus controller 7 fetches the macroinstructions from the external memory (not shown), responsive to a fetch demand for the macroinstructions from the decoder 3 and it also transfers the macroinstructions thus feched to the buffer 9 in the decoder 3 via the internal bus 500. Moreover, the bus controller 7, when the use of the external data bus 100 is demanded at the same time by the decoder 3 and the instruction execution unit 5, adjusts or coordinates these demands in accordance with the priority orders preliminarily established. In order to realize high speed instruction execution, the priority of the use of the external data bus relating to the normal instruction execution is normally higher than that of the macroinstruction fetch. However, this is only the case when simultaneous demands for the use of the bus occur. Accordingly, even when any demand for the use of the external data bus 100 involving the instruction execution having a higher priority occurs, the use of the external data bus 100 involving the instruction execution has to be delayed until the use of the bus 100 by the macroinstruction fetch having a lower priority order terminates when the external data bus 100 is being used for the macroinstruction fetch.
In the microprocessor in the prior art thus constructed, when the instruction which has been read out of the buffer 9 provided within the decoder 3 and decoded by the decoder, belongs to an unconditional branch instruction, it is normal that a plurality of macroinstructions which have already been stored in the buffer 9 are all processed as being invalid in order to execute instructions at the branch destination and the latter is then fetched and is newly stored in the buffer 9.
As described in the foregoing prior art, in the microprocessor for carrying out the instruction execution in such a manner that the macroinstructions are preliminarily locked-ahead and are temporarily stored in the buffer 9 within the decoder 3, the subsequent macroinstructions which have been stored are all made invalid when the instructions to be decoded and executed belong to unconditional branch instructions and the instructions at the branch destination are to be executed. Accordingly, in the case described above, although all of the macroinstructions stored in the buffer 9 are made invalid, an unnecessary operation that they are to be decoded by the decoder was performed. As a result, an combined circuit such as PLA (Programmable Logic Array) which performs the decoding operation is operated uselessly, thus increasing power dissipation and calorific value.
In addition, due to the non-effective macroinstruction fetch through the external data bus which results in the useless instruction storing in the buffer 9 and the useless instruction decoding in the decoder, other operations for the instruction execution via the data bus are hindered and the use of the bus 100 has to be delayed until the useless fetch operation terminates, thus delaying the execution of the other useful instructions.